Anuradha Aravalli

314 Aryabhatta Marg	aa@anuradha-aravalli.com
Andheri(W), Bombay 400063, India	http://www.anuradha-aravalli.com
Tel: +91-22-314159267

Interest
Compilers and parallel computation

Education
PhD Computer Science, UC Santa Barbara, Santa Barbara, CA. 1998
M.Tech Computer Science, IIT Bombay, India, 1994
BE Computer Science, University of Rourkee, India, 1992

Experience
Staff Software Engineer, Better Search Engine, Inc April 2001 - July 2003

Speedup Index Push June 2003 - July 2003
- Designed and implemented global scheduling for file distribution system that extended its capacity by 10x.
- This improvement plus others speedup index push to all data centers by 3x. This also allowed us to bring European Datacenter online without much disruption and scaled smoothly when we transitioned to higher bandwidth connections. Other than crawl, the ads and other groups also benefited from theses changes.
Build/Deploy New Crawl System December 2001 - December 2002
- Build URL status server and scheduler to help support when to crawl what. Status also record reasons for failures to facilitate debugging.
- Added verification of url related information throughout the system to guard against hardware and software bugs.
- Hooked up new duplicate detection system, and debugged performance bottleneck via connection multiplexing.
Improve Indexing Performance April 2001 - December 2001
- Sped up various part of indexing system: by batched RPC updates, futher parallelized duplicate detection system, added pull/get to sorter to avoid extra disk access, improved canonicalization, and reorganized indexing dependencies to shorten critical paths. This work reduced overall indexing time by 12%.
Malloc Performance April 2001
- Discovered and fixed an off-by-1 bug in malloc library that kept many applications from allocating closer to 2GB of memory.

Senior Software Engineer, VeriFast, Inc December 1998 - December 2000

Model Checker December 1998 - December 2000
- Developed one of the two verfication engines (~36000 lines of C++ code) with a strong focus on both memory and time performance optimizations, such as lazy evaluation and operation reordering.
- Profiled and optimized the performance on other parts of this verification software. For example, developed a DAG (directed acyclic graph) based algorithm to replace the pre-existing tree-based algorithm for circuit modeling. This new algorithm reduced the memory usage by 500MB for certain customer verification problems.
Open Verilog International (OVI) June 2000 - December 2000
- OVI Committee member to help define Circuit Verification language.

Selected Publications
omitted

Honors

Keynote speaker at the "23rd International Workshop on Very Large Scale Data Storage Networks", Barcelona, July 2003.
Best poster award at IJCPDLS-99.
IEEE Rourkee-branch Award for best undergraduate thesis. 1992.
National (Indian) Talent Search Scholarship in 1988.

References
omitted